About this job
Roles and Responsibilities: System Verilog ( SV) , HVL Verification, Verification Planning and Tracking, Hardware Modelling Skill & Job Requirements: - - >HVL Verification( L4) - Good Understanding of HVL concepts. Able to code test scenario using existing Hadditional scenarios. Able to build HVL test benches for simple designs. Competmodules based on coverage plan. Able to plan, implement & debug assertions. Ablverification components in HVL environment. e. g Sub system or Full chip Level. HVL Verification IPs, requirement analysis of the test bench. Implementation o - - >Verification Planning and Tracking( L3) - Understanding of verification and coverage plans - able to extract testscenarios from the plan. Competent enough to come- out with the verificationplan for the unit level verification. Competent enough to come- out with theverification plan for the system level verification - and track theverification progress. - - >Hardware Modelling( L1) - Able to Model hardware blocks using C / C++. Able to integrate such models fordesign verification and as a building block for a virtual platform. Has a goodunderstanding of RTL co verification and model cycle accuracy concepts. - - >System Verilog ( SV) ( L2) -
Education:(UG - B.Tech/B.E. - Any Specialization) AND (PG - Post Graduation Not Required) AND ( Doctorate - Any Doctorate - Any Specialization, Doctorate Not Required)
Experience years: 3 to 5 yrs.
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