About this job
Standard cells for basic cells to complex cells
SRAM compiler and full custom memories (macro/ block/leaf cells)
Experience and familiarity in various physical verification checks - DRC, LVS, ERC, EM, etc.
Not Disclosed by Recruiter
Embedded, EDA, VLSI, ASIC, Chip Design
Programming & Design
Analog Design, memory layout, mixed signal, circuit design, Standard cell layout, DRC, LVS, ERC, EM, pdk / pas, perl, shell
4+yrs of Exp with Standard cells for basic cells to complex cells
SRAM compiler and full custom memories (macro/ block/leaf cells
Should have understanding and working knowledge of good layout practices for lower process nodes 22nm, 28nm and 45nm.
Experience years: 4 to 9 yrs.
How to apply