About this job
Transport Front End Verification-Senior Engineers/Staff
· This individual will be a key member of the ASIC system level verification
team. ASIC/FPGA verification using advanced verification concepts and
environments ie OVM/UVM and System Verilog, on both module level and chip level
with the use of constrained random verification techniques
· The successful candidate will be involved in hands-on implementation work for
every aspect of ASIC verification, working closely with the system group,
architects, designers and verification teams.
· The successful candidate should have experience in going through several
complete and successful ASIC Design/Verification cycles from architecting and
creating of ASIC test environment (communications/networking related
preferred)to full completion of the verification work.
· Knowledge of communications protocols an asset: OTN, Ethernet, Sonet, GFP,
Error Correction Codes
2-7, 7-12 years of hands-on design/Verification experience
· Defining, developing test plans , running regressions, generating coverage
metrics and providing automated status.
Strong debugging skills a must. Must have good communication skills and the
ability and desire to work as a team
Background in communications/networking a plus.
Experience years: 5 to 10 yrs.
How to apply
Contact Company:The Human Capital