Equivalent Circuit for the MOSFET
When we attempt to draw an equivalent circuit of a MOSFET, we find that in addition to the intrinsic MOSFET itself, there are a variety of parasitic elements
associated with it.
Equivalent Circuit:
- An important addition to the gate capacitance is the so-called Miller overlap capacitance due to the overlap between the gate and the drain region that is shown in figure. This capacitance is particularly problematic because it represents a feedback path between the output drain terminal and the input gate terminal.
- One can measure the Miller capacitance at high frequency by holding the gate at ground (VG - 0) so that an inversion layer is not formed in the channel.
- Thereby, most of the measured capacitance between gate and drain is due to the Miller capacitance, rather than the gate capacitance Ci. It is possible to minimize this capacitance by using a so-called self-aligned gate.
- In this process, the gate itself is used to mask the source/drain implants, thereby achieving alignment. Even in this design, however, there is still a certain amount of overlap because of the lateral straggle or spread of the implanted dopants underneath the gate, further exacerbated by the lateral diffusion which occurs during high temperature annealing.
Effective Channel Length:
This spread of the source/drain junctions under the gate edge determines what is called the channel length reduction, ΔLR that is shown in figure (2). Hence, we get the electrical or "effective" channel length, Leff, in terms of the physical gate length, L as
There can also be a width reduction, ΔZ, which changes the effective width, Zeff, from the physical width Z of the MOSFET. The width reduction results from the electrical isolation regions that are formed around all transistors, generally by LOCOS. Another very important parameter in the equivalent circuit is the
source/drain series resistance, RSD = (Rs RD), because it degrades the drain current and transconductance. For a certain applied drain bias to the source/
drain terminals, part of the applied voltage is "wasted" as an ohmic voltage drop across these resistances, depending on the drain current (or gate bias).
Hence, the actual drain voltage applied to the intrinsic MOSFET itself is less; this causes ID to increase sub-linearly with Vc. We can determine RSD, along with ΔLR, from the overall resistance of the MOSFET in the linear region,