MOSFET: Drain-Induced Barrier Lowering
If small channel length MOSFETs are not scaled properly, and the source/drain junctions are too deep or the channel doping is too low, there can be unintended electrostatic interactions between the source and the drain known as Drain- Induced Barrier Lowering (DIBL).
Operation of DIBL:
- The phenomenon can be understood from Fig. given below, where we have schematically plotted the surface potential along the channel for a long channel device and a short device.
- We see that as the drain bias is increased, the conduction band edge (which reflects the electron energies) in the drain is pulled down, and the drain channel depletion width expands.
- For a long channel MOSFET, the drain bias does not affect the source-to-channel potential barrier, which corresponds to the built-in potential of the source-channel p-n junction.
- Hence, unless the gate bias is increased to lower this potential barrier, there is little drain current. On the other hand, for a short channel MOSFET, as the drain bias is raised and the conduction band edge in the drain is pulled down (with a concomitant increase of the drain depletion width), the source-channel potential barrier is lowered due to DIBL.
- This can be shown numerically by a solution of the two dimensional Poisson equation in the channel region. Simplistically, the onset of DIBL is sometimes considered to correspond to the drain depletion region expanding and merging with the source depletion region, and causing punchthrough breakdown between source and drain.
- However, it must be kept in mind that DIBL is ultimately caused by the lowering of the source-junction potential barrier below the built-in potential. Hence, if we get DIBL in a MOSFET for a grounded substrate, the problem can be mitigated by applying a substrate reverse bias, because that raises the potential barrier at the source end
- This works in spite of the fact that the drain depletion region interacts even more with the source depletion region under such back bias.
- Once the source-channel barrier is lowered by DIBL, there can be significant drain leakage current, with the gate being unable to shut it off.
Solution of this problem:
The source/drain junctions must be made sufficiently shallow (i.e., scaled properly) as the channel lengths are reduced, to prevent DIBL. Secondly, the channel doping must be made sufficiently high to prevent the drain from being able to control the source junction. This is achieved by performing what is known as an anti-punchthrough implant in the channel.
Sometimes, instead of such an implant throughout the channel (which can have undesirable consequences such as raising the VT or the body effect), a localized implant is done only near the source/drains. These are known as halo or pocket implants. The higher doping reduces the source/drain depletion widths and prevents their interaction.
For short channel MOSFETs, DIBL is related to the electrical modulation of the channel length in the pinch-off region, ΔL. Since the drain current is inversely proportional to the electrical channel length, we get
for small pinch-off regions, ΔL. We assume that the fractional change in the channel length is proportional to the drain bias,
where λ is the channel length modulation parameter. Hence, in the saturation region, the expression for the drain current becomes