Dataflow Modeling-Delta Delay Revisited
The following section explains the Delta Delay Revisited.
Overview of the Delta Delay Revisited:
- In a signal assignment statement, if no delay is specified or a delay of 0ns is specified, a delta delay is assumed.
- Delta delay is an infinitesimally small amount of time.
- It is not a real time delta and does not cause real simulation time to change.
- The delta delay mechanism provides for ordering of events on signals that occur at the same simulation time. Consider the circuit shown in Fig. 1.1 and its corresponding model that follows.
Figure 1.1 Three inverting buffers in series
entity FAST_INVERTER is
port (A: in BIT; Z: out BIT); end;
architecture DELTA_DELAY of FAST_INVERTER is
signal B, C: BIT;
begin -- Following statements are order independent :
Z <= not C; - signal assignment #1
C <= not B; - signal assignment #2
B <= not A; - signal assignment #3
- The three signal assignments in the FAST_INVERTER entity use delta delays.
- When an event occurs on signal A, say at 20 ns, the third signal assignment is triggered which causes signal B to get the inverted value of A at 20ns 1Δ.
- When time advances to 20ns 1Δ, signal B changes.
- This triggers the second signal assignment, causing signal C to get the inverted value of B after another delta delay, that is, at 20ns 2Δ. When simulation time advances to 20ns 2Δ, the first signal assignment is triggered causing Z to get a new value at time 20 ns 3Δ.
- Even though the real simulation time stayed at 20 ns, Z was updated with the correct value through a sequence of delta-delayed events.
- This sequence of waveforms is shown in Fig. 1.2.
Figure 1.2 Delta delays in concurrent signal assignment statements.