Safe operating areas of a Power Transistor
Safe operating areas of a Power Transistor:
Fig: Safe operating areas of a Power Transistor.(a) FBSOA; (b) RBSOA
- In the hard saturation region base current loses control over the collector current which is determined entirely by the collector load and the biasing voltage VCC. This behavior is similar to what happens in a signal transistor except that the drift region of a power transistor continues to offer a small resistance even when it is completely shorted out (by excess carrier injection from the base).
- For larger collector currents the collector-emitter voltage drop is almost proportional to the collector current. Manufacturers usually provide the plots of the variation of VCE (sat) vs. iC for different values of base current and junction temperature. Curves showing the variation of VCE (sat) with iB for different values of iC and junction temperature are also provided by certain manufacturers.
- Applicable operating limits on a power transistor are compactly represented in two diagrams called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating Area. (RBSOA) applicable to iB > 0 and iB ≤ 0 conditions respectively.
- The horizontal upper limit of the FBSOA is determined by the maximum allowable collector current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor does not have any appreciable reverse voltage blocking capacity they are usually not used in ac circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of the collector current waveform should not exceed this limit.
- The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the maximum allowable power dissipation and maximum junction temperature. Since FBSOA is shown on a log-log scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines. This limit is different for dc and pulsed operation due to the thermal time constant of the device. The “DC” limit is applicable to the average power loss if the transistor remains continuously in the conduction state (active, quasi saturation or saturation).
- The third limit of the FBSOA (red line) arises due to the “second break down” failure mode of a Power transistor. It shows the limiting combinations of collector voltage and current so that second break down does not occur. On the log –log scale of the FBSOA this limit also appears as a straight limit. Like the maximum power dissipation limit, the second break down limit is also different for “DC” and “Pulsed” operation of different pulse durations. The interpretation of the pulse duration corresponding to a particular limit is also same.
- The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage (VSUS) of the transistor and appears as a vertical line in the FBSOA at VCE = VSuS .The FBSOA of a Power transistor is given at a specified case temperature. Both the maximum power dissipation limit and the second break down limits are to be derated as per the derating characteristics provided by the manufacturers when the case temperature exceeds the specified value.
- The RBSOA is plotted on a linear scale and has a more rectangular shape. RBSOA is a switching SOA since a transistor cannot conduct current for any appreciable duration under reverse biased condition. It shows the limiting permissible combinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limit corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA.
- The right hand side vertical limit correspond the avalanche break down voltage of the transistor with reverse bias. If a negative voltage is applied across the BE junction the right hand side limit of the RBSOA increases somewhat to the value VCBO at low value of the collector current.