A Typical Circuit For Generation Of PWM Waveforms
A Typical Circuit for Generation of PWM Waveforms:
- As seen in the block diagram schematic circuit for generation of balanced sinusoidal signals, each EPROM output is fed to a D/A (Digital to Analog) converter to finally come up with analog value of Sin(Φ). Now in the D/A converter, the sign bit is not to be fed. The MSB input of D/A could be grounded.
- A separate simple logic circuit could take the MSB output of EPROM for sign changing of the D/A output. One such simple arrangement uses an analog switch, an op-amp and a few resistors to assign correct sign to the analog output of the D/A converter.
- An alternative arrangement for storing data in the EPROM could be to store [1 Sin(Φ)] value in the memory locations so that negative numbers are not encountered. While decoding the digital value into analog form (using Digital to Analog converter) the analog equivalent of this extra “1” may be subtracted using a simple Op-amp based subtractor circuit.
- In the circuit of schematic circuit for generation of balanced sinusoidal signals, a control voltage VC is applied to a voltage to frequency (V/f) converter. The V/f converter should preferably have a linear relation between the applied voltage and output frequency. The V/f converter output is fed as clock to a divide by 210 ripple counter circuit.
- Ten address lines for the 1K EPROM are connected to the ten output lines of the ripple counter. For a 2K EPROM eleven address lines are required and the appropriate counter would then be a divide by 211 counters.
- The consecutive clock pulses to the ripple counter increment the EPROM’s address word sequentially, pointing to the next EPROM memory location after each clock. The EPROM outputs data of the addressed memory location asynchronously. Since the SINE wave data is loaded in the EPROM sequentially, the digital value of SINE wave is output by the EPROM in the correct sequence.
- The D/A converter then converts the EPROM output into an analog signal. The SINE wave output by D/A converter is however only a stepped approximation of the continuous SINE wave but the number of steps per sine-wave cycle being large (=612), the resolution is sufficient for the present purpose. The Address lines for the two EPROMs are tied together. Thus when, say, first memory location of EPROM#1 is addressed the first location of EPROM#2 is also simultaneously addressed.
- The SINE waves stored in the two EPROMs are phase shifted by 1200 and hence the corresponding D/A converters output 1200 shifted SINE waves. The ten-bit address word generated by ripple counter repeats after 1024 counts and accordingly SINE wave data from the EPROMs are also repeated after 1024 counts (this count represents one output cycle time period of the sinusoidal modulating wave).
- The rate at which the address bus data changes decides the frequency of the output waveform, which eventually is controlled by the control voltage VC. D/A converters have reference voltage ( VRef and - VRef) pins provided for setting the maximum and minimum excursion of the output voltage waveform. In the circuit of schematic circuit for generation of balanced sinusoidal signals, it is assumed that -V Refpins are grounded and VRef pins are connected to the reference voltage ‘VM’. Thus ‘VM’ decides the magnitude of analog sinusoidal signal output by the D/A converter. The magnitude control signal ‘VM’ may be tied to frequency control signal ‘VC’ and one may achieve proportional change in inverter’s output voltage and frequency.
- The circuit in Schematic circuit for generation of balanced sinusoidal signals produces two SINE waveforms having identical magnitude and frequency but phase shifted by 1200. The third modulating SINE wave could be generated simply by adding these two waveforms followed by a sign inversion. [Sin(Φ) Sin(Φ-1200) = - Sin(Φ-2400)]. Thus a simple circuit using a couple of op-amps will get the third SINE wave.
- High frequency triangular carrier waveform generator and comparator etc. are pretty simple circuits to realize. The comparator output gives the required PWM pattern. The output frequency (as well as magnitude) can be varied in an open-loop or closed-loop by varying the control voltages V Cand VM.