Selective Harmonic Elimination Technique:

• It is known that some selected harmonics could be eliminated from the inverter output voltage by introducing notches at suitable time instants (angles) in the pole voltage waveform.

•  To eliminate more number of unwanted harmonics from the output one needs to have more notches per output cycle.

•  For the required magnitude of output voltage and frequency and the inverter’s dc bus voltage, these notch angles need to be calculated off-line using digital computer and later used for generating the switching sequence.

•  The notch angle information for all three phases taken together can be converted into a matrix of switching word for the inverter. The consecutive switching word information at short and regular time interval (in time steps of, say, 10 microseconds) is stored for a full output cycle in consecutive locations of a memory device, like, EPROM.

• To output the proper switching signal these stored values are output sequentially by sequentially incrementing the address word of the EPROM. The time rate at which the address changes should be identical to the time rate at which the information was stored.

• The switching word information is then converted into gate control signals for the inverter switches. As the inverter’s input and output parameters change, the switching matrix changes too. For an inverter producing variable voltage, variable frequency output the total requirement of memory size becomes large. However the cost of memory chips is coming down and hence the scheme is one of the preferred PWM schemes.

Current Controlled PWM (CCPWM) Technique:

• In current controlled PWM (CCPWM) technique, reference load current (as desired by the user) signals are generated and the inverter switches are controlled so that the actual inverter phase currents match these within tolerable error limits.

• The scheme requires current sensors to sense actual phase currents. For a three-phase load, sensing two phase-currents suffices as the third phase current can be obtained by algebraic manipulation of the other two. The actual currents are compared with the corresponding reference currents to generate the required switching action.

•  Most often hysteresis type bang-bang controllers are used. To increase the magnitude of current leaving the inverter pole (and entering the load terminal), the high side switch of the particular pole is turned on. Conversely the low side switch is turned on to decrease the magnitude of load current.

• Turning of high side switch causes input dc voltage to support the load phase current. The load phase current flows against the input dc voltage when low side switch is ON. The control actions for individual legs are generally independent of each other but the rate at which current changes in one leg may get affected by the switching state of the other legs.

• The control required is simple and the load current is directly controlled, hence the name CCPWM. The necessity of two numbers of fast current sensors may be seen as a drawback but current sensor costs are coming down and most inverter circuits employ current sensors, anyway, for protection against over-current. Another drawback of the scheme may be associated with the hysteresis controller, if used.

• The switching frequency of such controllers becomes dependent on load parameters and may not remain optimum for the given load. There are, however, other control schemes for CCPWM inverter where the switching frequency can remain fixed in spite of load parameter changes.

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