PSK Error Performance
The bit error performance is related to the distance between points on a signal state-space diagram.
QPSK and BPSK error performance:
- For example, on the signal state-space diagram for BPSK shown in Figure 2.39a, it can be seen that the two signal points (logic 1 and logic 0) have maximum separation (d) for a given power level (D).
- The figure shows, a noise vector (VN), when combined with the signal vector (Vs), effectively shifts the phase of the signaling element (VSE) alpha degrees.
- If the phase shift exceeds 90°, the signal element is shifted beyond the threshold points into the error region.
- For BPSK, it would require a noise vector of sufficient amplitude and phase to produce more than a ±90° phase shift in the signaling element to produce an error.
- For PSK systems, the general formula for the threshold points is
where M is the number of signal states
- The phase relationship between signaling elements for BPSK (i.e., 1800 out of phase) is the optimum signaling format, referred to as antipodal signaling, and occurs only when two binary signal levels are allowed and when one signal is the exact negative of the other.
- Because no other bit-by-bit signaling scheme is any better, antipodal performance is often used as a reference for comparison
- The error performance of the other multiphase PSK systems can be compared with that of BPSK simply by determining the relative decrease in error distance between points on a signal state-space diagram
- For PSK, the general formula for the maximum distance between signaling points is given by
d = error distance
M = number of phases
D = peak signal amplitude