Digital System Design
VHDL
Combinational Circuit Design
Sequential Circuits Design
Complex sequential systems
- Introduction to VHDL.
- VHDL Capabilities.
- VHDL-Hardware Abstraction.
- VHDL-Design Units
- VHDL-Entity Declaration.
- Architecture Body-Structural Style of Modeling
- Architecture Body-Dataflow Style of Modeling
- Architecture Body- Behavioral Style of Modeling
- Architecture Body- Mixed Style of Modeling
- Configuration Declaration
- Package Declaration
- Package Body
- Model Analysis
- VHDL-Basic Language Elements- Identifiers
- VHDL-Basic Language Elements-Data Objects
- VHDL-Data Types
- Data Types-Scalar Types
- Data Types-Scalar Types-Enumeration Types
- Data Types-Scalar Types-Integer Types
- Data Types-Scalar Types-Floating Point Types
- Composite Type-Array Types
- Record Types
- Record Types
- Access Types
- Incomplete Types
- File Types
- Operators
- Behavioral Modeling-Entity Declaration
- Behavioral Modeling-Architecture Body
- Behavioral Modeling-Process Statement
- Behavioral Modeling-Variable Assignment Statement
- Behavioral Modeling-Signal Assignment Statement
- Behavioral Modeling-Wait Statement
- Behavioral Modeling-If Statement
- Behavioral Modeling-Case Statement
- Behavioral Modeling-Null Statement and Loop Statement
- Behavioral Modeling- Next Statement and Exit Statement
- Behavioral Modeling-Assertion Statement
- Behavioral Modeling- Inertial Delay Model and Transport Delay Model
- Behavioral Modeling-Signal Drivers
- Behavioral Modeling-Effect of Transport Delay on Signal Drivers
- Effect of Inertial Delay on Signal Drivers
- Multiple Processes
- Dataflow Modeling-Concurrent Signal Assignment Statement
- Dataflow Modeling-Delta Delay Revisited
- Dataflow Modeling- Conditional Signal Assignment Statement
- Dataflow Modeling-Selected Signal Assignment Statement
- Dataflow Modeling-Concurrent Assertion Statement
- Dataflow Modeling-Block Statement
- Structural Modeling-Component Declaration
- Structural Modeling-Component Instantiation
- Structural Modeling- Resolving Signal Values
- Packages-Package Declaration
- Packages-Package Body
- Design Libraries
- Design File
- Implicit and Explicit Visibility
- Explicit Visibility-Library Clause and Use Clause
- Subprograms
- Functions
- Procedures
- Subprogram declaration
- Subprogram Overloading
- Operator Overloading
- Generics
- Generics-value Specification
- Configuration Specification
- Configuration Declaration
- Entities and architectures.
- Identifiers, spaces and comments.
- Combinational building blocks-Three-state buffers
- Combinational building blocks-Three-state buffers
- Combinational building blocks-Standard logic package
- Decoders-2 to 4 decoder
- Seven-segment display
- n to 2n decoder – shift operators
- Multiplexers-4 to 1 multiplexer
- Priority encoder
- Priority encoder- Sequential VHDL
- Adders-Functional model
- Ripple adder-Functional model
- Parity checker
- Attributes
- Synchronous sequential systems
- Design of a three-bit counter
- SR latch
- D latch
- Edge-triggered D flip-flop
- Asynchronous set and reset
- Rising_edge and falling_edge
- Synchronous set and reset and clock enable
- JK and T flip-flops
- Multiple bit register
- Shift registers-Serial in parallel out
- Universal shift register
- Binary counter
- Ripple counter using T flip-flops
- Johnson counter
- Linear feedback shift register
- ROM
- Static RAM
- DRAM
- Synchronous RAM
- Sequential multiplier
- Aliases
- Asymmetric clock
- Random pulse generator
- Checking responses with assert statements