all notes based on according to following syllbus
Register Transfer Language, Bus and Memory Transfers, Bus Architecture, Bus Arbitration,
Arithmetic Logic, Shift Microoperation, Arithmetic Logic Shift Unit, Design of Fast address,
Arithmetic Algorithms (addition, subtraction, Booth Multiplication), IEEE standard for Floating
Hardwired & Micro Programmed (Control Unit): Fundamental Concepts (Register Transfers,
performing of arithmetic or logical operations, fetching a word from memory, Storing a word in
memory), Execution of a complete instruction, Multiple-Bus organization, Hardwired Control,
Micro programmed control(Microinstruction, Microprogram sequencing, Wide-Branch
addressing, Microinstruction with Next-address field, Prefetching Microinstruction).
Processor Organization: General register organization, Stack organization, Addressing mode,
Instruction format, Data transfer & manipulations, Program Control, Reduced Instruction Set
I/O Interface, Modes of transfer, Interrupts & Interrupt handling, Direct Memory access, Input-
Output processor, Serial Communication.
Memory Hierarchy, Main Memory (RAM and ROM Chips), organization of Cache Memory,
Auxiliary memory, Cache memory, Virtual Memory, Memory management hardware.
Unit – V(8L)
Parallel Processing, Pipelining- Arithmetic Pipelining, Instruction Pipelining, RISC Pipelining,
Vector Processing, Array Processor. Multiprocessor: Characteristic of Multiprocessor,
Interconnection Structure, Interprocessor Arbitration, Cache Coherence
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