Design of 14-bit, 100 MSPS, Dual channel pipelined A/D converter IC can be used for Intermediate Frequency (IF) Analog Front-End (AFE) in communication systems. Moreover some of the data acquisition systems also need high speed, high accuracy data converters where faster data requirements are needed (viz. Ultrasound sensors etc). In terms of frequency, MDAC is a very critical block to meet the high sampling requirements of ADC. Unity Gain Bandwidth (UGB) of the Operational Transconductance Amplifier (OTA) for MDAC requires high fT for the transistor. UMC 130nm is preferable technology to meet 100 MSPS speed and possible scale up of sampling frequency for future versions. Hence this IC is being designed using UMC 0.13-Ķ CMOS technology. The converter is implemented with 6 stage pipeline architecture. The design is based on switch-capacitor circuitry. Each stage consists of a residue OTA, differential comparators (sub-ADC) and a sub-DAC. The converter accepts +/- 1V fully differential signal up to 100MHz. The digital output from every stage is digitally corrected to obtain a 14+1 bit (Extra sign bit) final output.