Secrecy is certainly important to the security or integrity of information transmission. Indeed, the need for secure communication is more profound than ever, recognizing the fact that conduct of much of our commerce, business and personal matters is ever being carried out today through the medium of computers, which has replaced the traditional medium computers.

Recently, the number of individuals and organizations using wide computer networks for personal and professional activities has increased a lot. Among them, there are several applications highly sensitive to data security such as commercial exchange on the Internet and smart cards. A cryptographic algorithm is an essential part in network security.

A well-known cryptographic algorithm is the Data Encryption Standard (DES) and which is widely adopted in security products. However, serious considerations arise from long-term security because of the relatively short key word length of only 56 bits and recently from the highly successful cryptanalysis attack.

Another cryptographic algorithm is International Data Encryption Algorithm (IDEA) and, which is considered one of the most important post-DES cryptographic algorithms due to its high immunity to attacks. The IDEA algorithm overcomes the problems of DES algorithm. IDEA is highly secure. As key lengths increase, the number of combinations that must be tried for a brute force attack increase exponentially. For example a 128-bit key would have 2^128 (3.402823669209e+38) total possible combinations.

In this paper, we present a VLSI implementation of the IDEA block cipher using VHDL using AMI 0.5 process technology standard cells. We have optimized the modulus multiplier and exploited the temporal parallelism available in the IDEA algorithm. In our implementation, the sub keys are generated internally once the original key is fetched. This key is retained unless a new key is used for encryption. This implementation does not employ additional RAM to store the sub keys, which is a significant improvement in area. Our chip contains the same eight units, and each unit can execute one round of the algorithm. Using pipelined design, eight rounds of the algorithm are executed in parallel in a chip. Our implementation operating at 10 MHz achieves a throughput of greater than 700 Mbps, which is several times higher than previous implementations.



Detailed report on IDEA & Its Implementation In VLSI can b e found in the attachment below