Introduction : The absence of a clock signal or clock circuit in asynchronous circuits causes significant problems for testing. Not all state-holding elements change at the same time, which means that intermediate short lived states exist.
It is impossible to freeze the circuit at such states, unless scan latches are employed extensively. Races and hazards may occur if the transitions of PIs do not comply with the original specification of the circuit’s environment.
However, out-of-spec input sequences may be necessary for testing. Tests that are not guaranteed to be hazard free are useless. A fault can sometimes be detected and sometimes not, depending on which state the circuit stabilizes at.
Moreover, in order to guard against hazards even for valid input changes, redundancy is sometimes introduced. Generally, redundant logic is untestable.
The testing of the asynchronous circuits can be done by using the Scan Methods. The Scan Methods are of two different types.
They are –
1. Full Scan Method.
2. Partial Scan Method.
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