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1. System Architecture and Implementation of MIMO Sphere Decoders on FPGA.
2. FPGA Implementation and Verification of LDPC Encoder with Weight (3, 6) Approximate Lower Triangular Matrix.
3. A Novel approach for 2D Gaussian surround function implementation of FPGA with reduced On-chip memory utilization.
4. Design of a GF (64)-LDPC Decoder Based on the EMS Algorithm.
5. Fast pipelined AES algorithm implemented on Xilinx FPGA.
6. Reduced switching activity based low power test pattern generator implemented on FPGA.
7. Area efficient image compression with modified wavelet transform technique with Verilog
8. AMBA-AHB compatible memory controller implementation on FPGA using Verilog
9. A pipelined implementation of OFDM transmitter and receiver on reconfiguration platforms.
10. RISC CPU core implementation for FPGA based configuration SoC platform
11. Implementation of DS-CDMA for reconfiguration communication link.
12. Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18nm CMOS.
13. Design of Low Power Two Stage CMOS Operational Amplifier.
14. Delay Area Efficient Low Voltage FVF Based Current Comparator.
15. Implementation of Full Adder Cells using NP-CMOS and Multi-Output Logic Styles in 90nm Technology.
16. Implementation of Full Adder Cells using NP-CMOS and Multi-Output Logic Styles in 90nm Technology.
17. DESIGN of a TIQ COMPARATOR for HIGH SPEED and LOW POWER 4 BIT FLASH ADC.
18. DESIGN OF DIGITAL VIDEO WATERMARKING SCHEME USING MATLAB SIMULINK.
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