Digital Logic Design
Preface xv
How to Use This Book for Self-Study xix
Unit 1 Introduction
Number Systems and Conversion
Objectives 1
Study Guide 2
1.1 Digital Systems and Switching Circuits 6
1.2 Number Systems and Conversion 8
1.3 Binary Arithmetic 12
1.4 Representation of Negative Numbers 16
Addition of 2’s Complement Numbers 17
Addition of 1’s Complement Numbers 19
1.5 Binary Codes 21
Problems 23
Unit 2 Boolean Algebra
Objectives 27
Study Guide 28
2.1 Introduction 34
2.2 Basic Operations 35
2.3 Boolean Expressions and Truth Tables 37
2.4 Basic Theorems 39
2.5 Commutative, Associative, and Distributive Laws 40
2.6 Simplification Theorems 42
2.7 Multiplying Out and Factoring 44
2.8 DeMorgan’s Laws 47
Problems 48
Laws and Theorems of Boolean Algebra 55
Unit 3 Boolean Algebra (Continued)
Objectives 56
Study Guide 57
3.1 Multiplying Out and Factoring Expressions 62
3.2 Exclusive-OR and Equivalence Operations 64
3.3 The Consensus Theorem 66
3.4 Algebraic Simplification of Switching Expressions 68
3.5 Proving Validity of an Equation 70
Programmed Exercises 73
Problems 78
Unit 4 Applications of Boolean Algebra
Minterm and Maxterm Expansions
Objectives 83
Study Guide 84
4.1 Conversion of English Sentences to Boolean Equations 90
4.2 Combinational Logic Design Using a Truth Table 92
4.3 Minterm and Maxterm Expansions 93
4.4 General Minterm and Maxterm Expansions 96
4.5 Incompletely Specified Functions 99
4.6 Examples of Truth Table Construction 100
4.7 Design of Binary Adders and Subtracters 104
Problems 107
Unit 5 Karnaugh Maps
Objectives 116
Study Guide 117
5.1 Minimum Forms of Switching Functions 127
5.2 Two- and Three-Variable Karnaugh Maps 129
5.3 Four-Variable Karnaugh Maps 133
5.4 Determination of Minimum Expressions
Using Essential Prime Implicants 136
5.5 Five-Variable Karnaugh Maps 141
5.6 Other Uses of Karnaugh Maps 144
5.7 Other Forms of Karnaugh Maps 146
Programmed Exercises 147
Problems 152
Unit 6 Quine-McCluskey Method
Objectives 159
Study Guide 160
6.1 Determination of Prime Implicants 165
6.2 The Prime Implicant Chart 168
6.3 Petrick’s Method 171
6.4 Simplification of Incompletely Specified Functions 173
6.5 Simplification Using Map-Entered Variables 174
6.6 Conclusion 176
Programmed Exercise 177
Problems 181
Unit 7 Multi-Level Gate Circuits
NAND and NOR Gates
Objectives 184
Study Guide 185
7.1 Multi-Level Gate Circuits 190
7.2 NAND and NOR Gates 195
7.3 Design of Two-Level NAND- and NOR- Gate Circuits 197
7.4 Design of Multi-Level NAND- and NOR- Gate Circuits 200
7.5 Circuit Conversion Using Alternative Gate Symbols 201
7.6 Design of Two-Level, Multiple-Output Circuits 204
Determination of Essential Prime Implicants for
Multiple-Output Realization 206
7.7 Multiple-Output NAND- and NOR-Gate Circuits 208
Problems 208
Unit 8 Combinational Circuit Design
and Simulation Using Gates
Objectives 215
Study Guide 216
8.1 Review of Combinational Circuit Design 219
8.2 Design of Circuits with Limited Gate Fan-In 220
8.3 Gate Delays and Timing Diagrams 222
8.4 Hazards in Combinational Logic 224
8.5 Simulation and Testing of Logic Circuits 229
Problems 232
Design Problems 236
Unit 9 Multiplexers, Decoders, and Programmable
Logic Devices
Objectives 242
Study Guide 243
9.1 Introduction 250
9.2 Multiplexers 251
9.3 Three-State Buffers 253
9.4 Decoders and Encoders 256
9.5 Read-Only Memories 259
9.6 Programmable Logic Devices 263
Programmable Logic Arrays 263
Programmable Array Logic 266
9.7 Complex Programmable Logic Devices 268
9.8 Field-Programmable Gate Arrays 270
Decomposition of Switching Functions 271
Problems 274
Unit 10 Introduction to VHDL
Objectives 280
Study Guide 281
10.1 VHDL Description of Combinational Circuits 285
10.2 VHDL Models for Multiplexers 290
10.3 VHDL Modules 292
Four-Bit Full Adder 294
10.4 Signals and Constants 297
10.5 Arrays 298
10.6 VHDL Operators 301
10.7 Packages and Libraries 302
10.8 IEEE Standard Logic 304
10.9 Compilation and Simulation of VHDL Code 307
Problems 308
Design Problems 313

Unit 11 Latches and Flip-Flops
Objectives 317
Study Guide 318
11.1 Introduction 322
11.2 Set-Reset Latch 323
11.3 Gated D Latch 327
11.4 Edge-Triggered D Flip-Flop 328
11.5 S-R Flip-Flop 331
11.6 J-K Flip-Flop 332
11.7 T Flip-Flop 333
11.8 Flip-Flops with Additional Inputs 334
11.9 Summary 336
Problems 337
Programmed Exercise 345
Unit 12 Registers and Counters
Objectives 348
Study Guide 349
12.1 Registers and Register Transfers 354
Parallel Adder with Accumulator 356
12.2 Shift Registers 358
12.3 Design of Binary Counters 362
12.4 Counters for Other Sequences 367
Counter Design Using D Flip-Flops 370
12.5 Counter Design Using S-R and
J-K Flip-Flops 371
12.6 Derivation of Flip-Flop Input
Equations—Summary 374
Problems 378
Unit 13 Analysis of Clocked Sequential Circuits
Objectives 388
Study Guide 389
13.1 A Sequential Parity Checker 395
13.2 Analysis by Signal Tracing and Timing Charts 397
13.3 State Tables and Graphs 401
Construction and Interpretation of Timing Charts 406
13.4 General Models for Sequential Circuits 408
Programmed Exercise 412
Problems 416
Unit 14 Derivation of State Graphs and Tables
Objectives 427
Study Guide 428
14.1 Design of a Sequence Detector 431
14.2 More Complex Design Problems 435
14.3 Guidelines for Construction of State Graphs 439
14.4 Serial Data Code Conversion 444
14.5 Alphanumeric State Graph Notation 448
Programmed Exercises 449
Problems 456
Unit 15 Reduction of State Tables
State Assignment
Objectives 466
Study Guide 467
15.1 Elimination of Redundant States 474
15.2 Equivalent States 476
15.3 Determination of State Equivalence Using
an Implication Table 478
15.4 Equivalent Sequential Circuits 481
15.5 Incompletely Specified State Tables 483
15.6 Derivation of Flip-Flop Input Equations 484
15.7 Equivalent State Assignments 487
15.8 Guidelines for State Assignment 490
15.9 Using a One-Hot State Assignment 495
Problems 498
Unit 16 Sequential Circuit Design
Objectives 511
Study Guide 512
16.1 Summary of Design Procedure for Sequential Circuits 514
16.2 Design Example—Code Converter 515
16.3 Design of Iterative Circuits 519
Design of a Comparator 519
16.4 Design of Sequential Circuits Using ROMs and PLAs 522
16.5 Sequential Circuit Design Using CPLDs 525
16.6 Sequential Circuit Design Using FPGAs 529
16.7 Simulation and Testing of Sequential Circuits 531
16.8 Overview of Computer-Aided Design 536
Design Problems 538
Additional Problems 544
Unit 17 VHDL for Sequential Logic
Objectives 549
Study Guide 550
17.1 Modeling Flip-Flops Using VHDL Processes 554
17.2 Modeling Registers and Counters Using VHDL
Processes 558
17.3 Modeling Combinational Logic Using VHDL
Processes 563
17.4 Modeling a Sequential Machine 565
17.5 Synthesis of VHDL Code 572
17.6 More About Processes and Sequential Statements 575
Problems 577
Simulation Problems 588
Unit 18 Circuits for Arithmetic Operations
Objectives 591
Study Guide 592
18.1 Serial Adder with Accumulator 594
18.2 Design of a Parallel Multiplier 598
18.3 Design of a Binary Divider 602
Programmed Exercises 607
Problems 612
Unit 19 State Machine Design with SM Charts
Objectives 623
Study Guide 624
19.1 State Machine Charts 625
19.2 Derivation of SM Charts 630
19.3 Realization of SM Charts 635
Problems 640
Unit 20 VHDL for Digital System Design
Objectives 646
Study Guide 647
20.1 VHDL Code for a Serial Adder 650
20.2 VHDL Code for a Binary Multiplier 652
20.3 VHDL Code for a Binary Divider 662
20.4 VHDL Code for a Dice Game Simulator 664
20.5 Concluding Remarks 667
Problems 668
Lab Design Problems 671
A Appendices
A MOS and CMOS Logic 675
B VHDL Language Summary 681
C Tips for Writing Synthesizable VHDL Code 686
D Proofs of Theorems 689
E Answers to Selected Study Guide
Questions and Problems 691